1. Field of the Invention
The present invention generally relates to electronic clock circuits, specifically to a method and system for providing clock recovery from a high-frequency data signal, and more particularly to such a method and system that has reduced power dissipation, and acceptable cycle variation (jitter).
2. Description of Related Art
Electronic circuits that provide clock signals are used in a wide assortment of devices, and particularly in computer systems. Microprocessors and other computer components, such as random access memory (RAM), device controllers and adapters, use clock signals to synchronize various high-speed operations. These computer clock circuits often use a phase-lock loop (PLL) circuit to synchronize (de-skew) an internal logic control clock with respect to an external system clock.
A typical prior art PLL circuit 1 is shown in FIG. 1 and includes a phase/frequency detector (PFD) 2, a charge-pump 3, a low-pass filter 4, and a voltage-controlled oscillator (VCO) 5. Phase/frequency detector 2 compares two input signals, a reference signal fref (from the external system clock) and a feedback signal ffb, and generates phase error signals that are a measure of the phase difference between fref and ffb. The phase error signals (“UP” and “DOWN”) from detector 2 are used to generate control signals by charge-pump 3 which are filtered by low-pass filter 4 and fed into the control input of voltage-controlled oscillator 5. Voltage-controlled oscillator 5 generates a periodic signal with a frequency which is controlled by the filtered phase error signal.
The output of voltage-controlled oscillator 5 is coupled to the input ffb of phase/frequency detector 2 directly or indirectly through other circuit elements such as dividers 6, buffers (not shown) or clock distribution networks (not shown), thereby forming a feedback loop. If the frequency of the feedback signal is not equal to the frequency of the reference signal, the filtered phase error signal causes the frequency of voltage-controlled oscillator 5 to shift (upwards or downwards) toward the frequency of the reference signal, until voltage-controlled oscillator 5 finally locks onto the frequency of the reference; following frequency acquisition, phase acquisition is achieved in a similar manner. The output of voltage-controlled oscillator 5 is then used as the synchronized signal (for internal logic control).
In cases where the incoming data is a self-clocking bit stream, the comparator system may be used to extract (recover) the clock information from the data stream itself. Clock extraction for high-speed serial links is usually accomplished using a VCO with a center frequency N for extracting a clock from a serial data stream modulated at N bits/sec. The VCO may provide multiple phases for oversampling, as discussed in the article by Yang, et al., “A 0.5 um CMOS 4.0 Gbit/s Serial Link Transceiver with Data Recovery Using Oversampling,” IEEE JSSC Vol 33, No. 5 (May 1998), or more commonly offer just a single phase for direct detection. An example of a single phase D-type phase detector technique used for non-return-to-zero (NRZ) data is disclosed in the article by Boerstler, “Dynamic Behavior of a Phase-Locked Loop Using D-Type Phase Detector and Nonlinear Voltage-Controlled Oscillator”, IBM Technical Report TR 21.1428 (Mar. 21, 1991).
For high-bandwidth applications such as in packet switches, maximizing both frequency and density simultaneously is desired, but this causes power dissipation and/or power density to be a significant problem. CMOS technology limitations can also limit the speed at which clock recovery can be accomplished, and operating the clocks at one-half the baud rate has been reported, as in Ewen et al., “Single-Chip 1062 Mbaud CMOS Transceiver for Serial Data Communication,” ISSCC Digest, Vol 38, pp. 32-33 (February 1995).
In light of the foregoing, it would be desirable to devise an improved method for recovering a high-speed clock from a data signal. It would be further advantageous if the method were to result in reduced power dissipation, while still ensuring acceptable levels of jitter.